The approach used to manufacture integrated circuits (ICs) on monolithic pieces of silicon substrate involves the fabrication of successive layers of insulating, conducting, and semiconducting materials. Each layer is patterned to form a structure that performs a specific function, usually linked with surrounding areas and subsequent layers. Therefore, the fabrication steps used to manufacture an IC must be executed in a specific sequence, which constitutes an IC process.
It is now the practice to fabricate multiple levels of conductive (typically metal) layers above a substrate. The multiple metallization layers accommodate higher densities as device dimensions shrink well below one micron design rules. Likewise, the size of interconnect structures will also need to shrink, in order to accommodate the smaller dimensions. Thus, as IC technology advances into the range below 0.25 microns, more advanced interconnect architecture is required.
One such architecture is a dual damascene integration scheme in which a dual damascene structure is used. The dual damascene process offers an advantage in process simplification by reducing the process steps required to form the vias and trenches for a given metallization level. The openings for the wiring of a metallization level and the underlying via connecting the wiring to a lower metallization level are formed at the same time. The procedure provides an advantage in lithography and allows for improved critical dimension control. Subsequently, both the via and the trench can be filled using the same metal-filling step, thereby reducing the number of processing steps required. The simplicity of the dual damascene process permits newer materials to replace cost-effectively the use of the existing aluminum-silicon dioxide scheme.
One such newer material is copper. The use of copper metallization improves performance and reliability over aluminum. Copper introduces additional problems, however, which are difficult to overcome when using known techniques for aluminum. For example, in conventional aluminum interconnect structures, a barrier layer is usually not required between the aluminum metal line and a silicon dioxide inter-level dielectric (ILD). When copper is used, copper must be encapsulated from the surrounding ILD, because copper diffuses or drifts easily into the adjoining dielectric. Once the copper reaches the silicon substrate, it will significantly degrade the performance of the device.
In the production of ICs upon semiconductor wafers or chips, the back end of production involves connecting all the fabricated semiconductor devices on the chip with electrically conductive materials. This back-end-of-line (BEOL) "wiring" step, which is the electrical connection scheme for connecting semiconductor devices, completes the circuits as designed to function within the total integrated circuit device. Metal lines are used in the metallization process as electrical connections between semiconductor devices.
In the fabrication of semiconductor devices, BEOL wiring often determines the function of the device. Therefore, BEOL processes are critical in semiconductor manufacturing. BEOL processes complete semiconductor fabrication in the final manufacturing steps. Errors due to faulty BEOL processes forfeit the entire production investment in the nearly completed device. As a result, device failure due to BEOL errors are very costly, and manufacturers strive to avoid BEOL defects.
A common BEOL process involves forming metal-insulator-metal (MIM) capacitors. Typically, these metallization structures are formed as diagrammed in FIGS. 1, 2, and 3. A multilevel structure is formed, as shown in FIG. 1, with a bottom metal layer 10, an interlayer dielectric 12, and a top metal layer 14 deposited sequentially on top of a substrate 8. Interlayer dielectric 12 is preferably an oxide and, more preferably, silicon dioxide. A photoresist pattern 16 is formed on the surface of the top metal layer as illustrated in FIG. 2.
Bottom metal layer 10, interlayer dielectric 12, and top metal layer 14 are simultaneously etched, as illustrated in FIG. 3, according to photoresist pattern 16 in a single etch step along direction arrow 17. An etch residue 18, which can poison the capacitor and render the capacitor useless, may form on interlayer dielectric 12 when bottom metal layer 10, interlayer dielectric 12, and top metal layer 14 (i.e., all three layers) are etched in a single etch step. Etch residue 18 on interlayer dielectric 12 offers an alternate electrically conductive path that can short the capacitor. Because the charge has an alternate path along the sidewall residue, the capacitor cannot function.
To overcome the shortcomings of conventional processes for forming multilevel metallization structures, a new integration scheme for MIM capacitors, is provided. An object of the present invention is to integrate a MIM capacitor into the dual damascene copper BEOL process without impacting wiring and via yield and parametrics. Other objects are to provide a process that yields reliable products while minimizing process cost and manufacturing steps. A related object is to provide a process that substantially eliminates the etch residue problem while forming a beneficial spacer (which contains contaminants and prevents the contaminants from breaking down the capacitor) around the bottom conductive plate. Still another related object is to provide a process that uses conventional semiconductor tooling.
It is still another object of the present invention to achieve a MIM structure for which the dielectric is scaleable in thickness, can be reworked (easily stripped and redeposited) without impacting wiring yield parameters, and can be one of several alternative materials. An additional object is to provide a modular process, i.e., a process having an set of steps independent of prior or subsequent processing steps. Yet another object of this invention is to provide a process that yields a planar or substantially planar capacitor structure, to avoid dielectric thinning over topography, and permits design of the capacitor structure in parallel or serial layouts.